This invention relates to technology which will be effective when applied to a semiconductor integrated circuit device which is a resin-mold package such as a QFP (Quad Flat Package), a SOP (Small Out-line Package), or a ZIP (Zigzag In-line Package), and which has a plurality of driving circuits (hereinafter referred to as "drivers").
A conventional semiconductor integrated circuit device is, for example, a resin mold package having a structure such as a QFP, a SOP, or a ZIP. Such a semiconductor integrated circuit device having a plurality of drivers includes a signal transmission side semiconductor integrated circuit LSI 100 and a signal reception side semiconductor integrated circuit device LSI 200 that are connected with intra-package transmission lines 300 (hereinafter referred to as an "interposer") as shown in FIG. 17.
In FIG. 17, reference numeral 101 represents a buffer of the transmission end LSI 100; 201 is a buffer of the reception end LSI 200; 301 is a driving-system signal line in the interposer 300, for example, a signal line for supplying clock signals; and 302 is a stationary-system signal line in the interposer 300, for example, a signal line for supplying pulse signals. Symbol Vcc represents a power source line (power source voltage line inside a chip: e.g., a circuit operating voltage of 5 V); Vss is a ground line (reference potential line inside the chip: e.g., a circuit ground potential of 0 V); Leff1 is an effective inductance on the power source Vcc side; Leff2 is an effective inductance on the power source Vss side; Vncc is a voltage drop (noise) due to the effective inductance Leff1 on the power source Vcc side effective inductance Leff1; Vnss is a voltage drop (noise) due to the effective inductance Leff2 on the power source Vss side; Vcr is a backward noise; Vcf is a forward noise; N is the number of driving-system signal lines 301 which are simultaneously switched; and Nr is the number of driving reception ends.
In FIG. 17, when four buffers 101 of the transmission end LSI 100 are simultaneously switched, a step voltage is applied to each of the four driving-system signal lines 301 of the intra-package transmission lines, and four buffers 201 of the reception end LSI 200 are driven.
To generate the step voltage at this time, a current change of di/dt per signal line occurs in the power source line Vcc. Since the N (N=4) driving-system signal lines 301 are simultaneously changed, the change is expressed by N.times.di/dt. The greater the number N, the greater becomes the current change. A voltage drop (noise) of Vnss=Leff1.times.N.times.di/dt occurs in the power source line Vcc due to the effective inductance Leff1 of all the lines through which the current of the power source line Vcc flows. This drop is also transmitted to the stationary-system signal line 302, and a cross-talk noise of the backward noise Vcr and the forward noise Vcf is superposed. Since the resultant noise exceeds the noise margin, an erroneous operation occurs in the stationary-system reception end LSI 200 or in the transmission end LSI 100.
Accordingly, the signal current becomes the current of the ground line Vss at the time of the drop of the step voltage, and the problem of the effective inductance Leff2 occurs. To reduce the voltage drops Vncc and Vnss irrespective of the increase of di/dt resulting from the increase of the number N and the higher operational speed, there is no way but to reduce the effective inductances Leff1 and Leff2. (Refer to "Microelectronics Packaging Handbook", VAN NOSTRAND REINHOLD, 1989, pp. 143-147.)
Consequently, for example, auxiliary electrode plate (for the power source Vss or the power source line Vcc) is disposed at opposed positions of the back of the semiconductor chip 2 and the inner lead 3 as shown in FIG. 18, so as to cut off a part of the electric field generated between the inner leads 3 by the auxiliary electrode plate (for the power source Vss or for the power source line Vcc) 5 and to reduce a stray capacitance added between the inner leads 3. In such a way, the cross-talk is reduced and the operation speed is increased.
Further, an auxiliary electrode plate 11 is disposed on the inner lead 3 through an insulating layer 7 as shown in FIG. 19. One of the ends of this auxiliary electrode plate 11 on the semiconductor chip 2 side is connected to the external terminal of the semiconductor chip 2 for the power source Vss (or for the power source Vcc) and the rear end of the auxiliary electrode plate 11 on the outer lead 4 side is connected to the rear end of the inner lead 3 for the power source Vss (or for the power source Vcc), so that the inductance component can further be reduced by the auxiliary electrode plate 11 and the operation speed can be increased (Japanese Patent Laid-Open No. 164056/1990).
In FIGS. 18 and 19, reference numeral 1 represents the resin mold semiconductor device; 2 is the semiconductor chip; 3 is the inner lead; 4 is the outer lead; 5, 6 and 11 are auxiliary electrode plate; 7 and 8 are the insulating layer; 9 is the bonding wire; 10 is the resin mold portion; 5A and 6A are connection portion; and 5B is a through-hole.